RT9595 ? ds9595-04 march 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wdfn-10l 3x3 mosfet integrated smart photoflash capacitor charger with igbt driver general description the RT9595 is a complete photoflash module solution for digital and film cameras. it is targeted for applications that use 2 to 3 aa batteries or 1 lithium-ion battery. the RT9595 adopts fly back topology which use constant primary peak current and zero secondary valley current to charge photoflash capacitor quickly and efficiently. the built-in 45v mosfet allows flexibility in transformer design and simplifies the pcb layout. the RT9595 also integrate an igbt driver for igniting photoflash tube. only a few external components are required, which greatly reduce the pcb space and cost. the RT9595 is available in the wdfn-10l 3x3 package. features z z z z z 45v mosfet integrated z z z z z charges any size photoflash capacitor z z z z z adjustable input current z z z z z adjustable output voltage z z z z z charge complete indicator z z z z z built-in igbt driver for igbt application z z z z z constant peak current control z z z z z over voltage protection z z z z z 10-lead wdfn package z z z z z rohs compliant and halogen free applications z digital still camera z film camera flash unit z camera phone flash gnd drvout charge drvin sw nc cs stat fb vdd 9 8 7 1 2 3 4 5 10 6 gnd 11 marking information fc=ym dnn fc= : product code ymdnn : date code RT9595 package type qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free)
RT9595 2 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram typical application circuit i peak maximum off enable stat cs gnd sw charge sq r + - 0.8v + - 1v fb vdd drvout drvin dcm sw sense ovp sw fb sw drvin fb drvout charge cs stat vdd sw RT9595 1 : n 2 4 8 7 10 6 3 5 strobe r3 c out + 100f/ 330v r1 1k r2 150k 150k v out gsd2004s igbt gate r4 1f 100k c1 v bat 47f 54k 3.3v/5v r cs c2 gnd 54k r5 gpio (floating/gnd) 1, exposed pad (11)
RT9595 3 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin n o. pin n ame pin function 1, 11 ( ex p osed pad ) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum p ower dissi p ation. 2 drvout igbt driver output pin. 3 vdd power input pin. 4 drvin igbt driver input pin. 5 ch arge charge enable pin. the charge function is executed w hen char ge pin is set from low to high. the chip is in shutdown mode when charge pin is set to low . 6 stat charge status output. open drain output. when target output voltage is reached, n-mosfet turns on. this pin needs a pull up resistor. 7 fb feedback voltage pin. 8 cs input c urrent setting pin. 9 nc no internal c onnection. 10 sw n-mosfet switching node. functional pin description recommended operating conditions (note 4) z drain source v oltage ----------------------------------------------------------------------------------------------------- 40v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply voltage, v dd ------------------------------------------------------------------------------------------------------ 6v z built-in n-channel enhancement mosfet drain-source voltage ----------------------------------------------------------------------------------------------------- 45v cs, charge, drvin, drvout, stat, fb ------------------------------- ------------------------------------------ 6v sw pulse current (pulse width 1 s) ----------------------------------------------------------------------------- 4a sw continuous current ------------------------------------------------------------------------------------------------- 2a z power dissipation, p d @ t a = 25 c wdfn-10l 3x3 ------------------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wdfn-10l 3x3, ja ------------------------------------------------------------------------------------------------------- 60 c/w wdfn-10l 3x3, jc ------------------------------------------------------------------------------------------------------- 7.5 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v
RT9595 4 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handlin g precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics (v dd = 3.3v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit vdd operating voltage v dd 2.9 -- 5.5 v switch off current i vdd_sw_off v fb = 1.1v -- 1 10 a shutdown current i off charge pin = 0v -- 0.01 1 a fb voltage v fb 0.985 1 1.015 v line regulation | v fb | 2.9v < v dd < 5.5v -- -- 10 mv stat open drain r ds(on) -- 11 19 charge enable high v ceh 1.3 -- -- v charge enable low v cel -- -- 0.4 v built-in n-channel enhancement mosfet drain-source on-resistance r ds(on) v dd = 3.3v, i d = 10ma -- 0.3 0.4 maximum off time during pre -charg e -- 9 -- s minimum off time -- 400 -- ns igbt driver drvin trip point 0.8 1.5 2.4 v drvout on resistance to v dd v dd = 3.3v -- 6 -- drvout on resistance to gnd v dd = 3.3v -- 11 -- propagation delay (rising) -- 20 -- ns propagation delay (falling) -- 200 -- ns
RT9595 5 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics output voltage vs. v bat 290 292 294 296 298 300 302 304 306 308 310 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v bat (v) output voltage (v) v dd = 3.3v 85 c 25 c ? 40 c charge time vs. v bat 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v bat (v) charge time (s) v dd = 5v, v out = 0 to 300v, c out = 140 f i pk-pri = 1.4a i pk-pri = 1.6a charging time time (1s/div) v dd = 3.3v, v bat = 3.7v, c out = 140 f stat (5v/div) i in (500ma/div) charge (5v/div) v out (200v/div) switching time (2.5 s/div) v dd = 3.3v, v out = 300v, v bat = 3.7v i pri (1a/div) i sec (200ma/div) v sw (20v/div) switching time (2.5 s/div) v dd = 3.3v, v out = 100v, v bat = 3.7v i pri (1a/div) i sec (200ma/div) v sw (20v/div) charge time vs. v bat 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v bat (v) charge time (s) v dd = 3.3v, v out = 0 to 300v, c out = 140 f i pk-pri = 1.4a i pk-pri = 1.6a
RT9595 6 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the RT9595 integrates a constant peak current controller for charging photoflash capacitor and an igbt driver for igniting flash tube. the photoflash capacitor charger uses constant primary peak current and sw falling control to efficiently charge the photoflash capacitor. pulling the charge pin high will initiate the charging cycle. however, the charge signal must come from low to high after v dd > 2v for at lease 1 s delay time. out min bat v n 40 v ? where : v out : target output voltage v bat : battery voltage where the i pk-pri is the primary peak current. users could select appropriate r cs according to the battery capability and required charging time. transformer the flyback transformer should be appropriately designed to ensure effective and efficient operation. 1. turns ratio the turns ratio of transformer (n) should be high enough so that the absolute maximum voltage rating for the internal n-mosfet drain to source voltage is not exceeded. choose the minimum turns ratio according to the following formula : pk_pri cs 40000 i (a) r = charge current setting the RT9595 simply adjusts peak primary current by a resistor r cs connecting to the cs pin as shown in the function block diagram. r cs determines the peak current of the primary n-mosfet according to the following equation : during mosfet on period, the primary current ramps up linearly according to v bat and primary inductance. a resistor connecting from cs pin to gnd determines the primary peak current. during the mosfet off period, the energy stored in the flyback transformer is boosted to the output capacitor. the secondary current decreases linearly at a rate determined by the secondary inductance and the output voltage (neglecting the voltage drop of the diode). the sw pin monitors the secondary current. when the secondary current drops to 0a, sw voltage falls, and then the mosfet on period starts again. the charging cycle repeats itself and charges the output capacitor. the output voltage is sensed by a voltage divider connecting to the anode of the rectifying diode. when the output voltage reaches the desired voltage set by the resistor divider, the charging block will be disabled and charging will be stopped. then stat pin will be pulled low to indicate the complete charging. the voltage-sensing path will be cut off when charging is completed to minimize the output voltage decay. both the charge and stat pins can be easily interfaced to a microprocessor in a digital system. -9 out pri pk-pri 400 10 v l ni 2. primary inductance each switching cycle, energy transferred to the output capacitor is proportional to the primary inductance for a constant primary current. the higher the primary inductance, the higher the charging efficiency. besides, to ensure enough off time for the output voltage sensing, the primary inductance should be high enough according to the following formula : v out : target output voltage n : transformer turns ratio i pk-pri : primary peak current vdd charge 2v >1s figure 1. recommend charge timing chart
RT9595 7 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pk-r out bat vv(nv) + the peak current of the diode equals the primary peak current divided by the transformer turn ratio as the following equation : pk-pri pk-sec i i n = where : n is the transformer turns ratio. output voltage setting the RT9595 senses the output voltage by a voltage divider connecting to the anode of the rectifying diode during off time as shown in figure 2. this eliminates power loss at voltage-sensing circuit when charging is completed. r1 to r2 ratio determines the output voltage as shown in the typical application circuit. the feedback reference voltage is 1v. out fb r1+r2 r1+r2 v v (1 ) and 299 r3 r3 =+ = it is recommended to set r3 = 1k and r1 = r2 = 150k for reducing parasitic capacitance coupling effect of the fb pin. r1 and r2 must be greater than 0805 size resistor for enduring secondary hv. another sensing method is to sense the output voltage directly as shown in figure 3. figure 2. sensing anode of diode figure 3. sensing output voltage r3 c out r1 1k r2 150k 150k v out fb r3 c out r1 66.5k r2 10m 10m v out fb c1 10nf over voltage protection (ovp) the RT9595 provides over voltage protection (ovp) function. in the typical application circuit, if the fb resistor r1, r2 or r3 is open, the fb voltage will be pulled low or floating. in this condition, when the charge pin goes high, the RT9595 begins switching, once the sw voltage rises to higher than 10v, the ovp function will be triggered. the avoiding ovp battery voltage upper limit is shown as the following equation : 3. leakage inductance the leakage inductance of the transformer results in the first spike voltage when n-mosfet turns off. the spike voltage is proportional to the leakage inductance and inductor peak current. the spike voltage must not exceed the dynamic rating of the n-mosfet drain to source voltage (45v). 4. transformer secondary capacitance any capacitance on the secondary can severely affect the efficiency. a small secondary capacitance is multiplied by n 2 when reflected to the primary will become large. this capacitance forms a resonant circuit with the primary leakage inductance of the transformer. therefore, both the primary leakage inductance and secondary side capacitance should be minimized. rectifying diode the rectifying diode should be with short reverse recovery time (small parasitic capacitance). large parasitic capacitance increases switching loss and lowers charging efficiency. in addition, the peak reverse voltage and peak current of the diode should be sufficient. the peak reverse voltage of the diode can be calculated as following equation : bat 0.16 (r1+r2+r3) v10v nr3 RT9595 8 ds9595-04 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature , t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wdfn-10l 3x3 packages, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-10l 3x3 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for wdfn-10l 3x3 package, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 6. recommended layout guideline gnd gnd gnd drvout charge drvin sw nc cs stat fb vdd 9 8 7 1 2 3 4 5 10 6 gnd 11 pgnd pgnd v out v bat bottom r cs figure 5. derating curve of maximum power dissipation 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wdfn-10l 3x3 four layers pcb layout consideration for best performance, the following guidelines should be strictly followed. ` both of primary and secondary power paths should be as short as possible. ` place the r cs as close to chip as possible. the gnd side of r cs should be directly connected to ground plane to avoid noise coupling. ` keep fb node area small and far away from nodes with voltage switching to reduce parasitic capacitance coupling effect. ` the pgnd should be connected to v bat ground plane to reduce switching noise. charge drvin drvout buf figure 4. trigger logic false triggering prevention the RT9595 includes a mechanism to prevent false triggering of drvout while the device is still in charging mode. with this mechanism, the drvin pin is only allowed to trigger drvout when the charge pin is low.
RT9595 9 ds9595-04 march 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
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